Electronic Verification Engineer

Job Description :

Duties:

• Driving improvements in methodology to achieve greater quality of verification;
• Recognize and write all types of coverage measures for stimulus and corner-cases;
• Responsible for the full life cycle of verification, from verification planning to test execution to collecting and closing coverage;
• Requirements:
• Bachelor Degree in Electronic Engineering;
• 2 years of relevant experience, less experience or fresh graduates are also welcomed;
• Experience with verification methodology such as UVM/OVM/VMM;
• Experience with SystemVerilog, Verilog and SVA